Two known technologies for reducing the parasitic capacitance generated in a semiconductor device are a technology where the permittivity of an insulating layer that covers a gate electrode or wiring is reduced and a technology where an insulating layer that covers a gate electrode or wiring is provided with a cavity (space) surrounding the gate electrode or wiring.
See, for example, the following documents.    Japanese Laid-open Patent Publication No. 11-274175    Japanese Laid-open Patent Publication No. 2009-272433    Japanese Laid-open Patent Publication No. 2015-204365
For a semiconductor device provided with an insulating layer that covers the gate electrode or wiring and has a cavity surrounding the gate electrode or wiring, when a further insulating layer is provided on top of the insulating layer, there is the risk of parasitic capacitance being generated due to this upper insulating layer, which would cause deterioration in the characteristics of the semiconductor device.